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description the A6280 is a 3 bit constant current led driver that has a wide range of output currents. the A6280 controls led luminance with a pulse width modulation (pwm) scheme that gives the application the capability of displaying a billion colors. the overall maximum current is set by an external resistor. the led luminance is controlled by performing pwm control on the outputs. the luminance data of the pwm signal for each led is stored in three 10 bit registers. each led can be dot corrected by a 7 bit scalar register that scales the maximum current from 100% down to 36.5%. all the internal latched registers are loaded by a 31 bit serial shift register. one bit is used to control the type of data loaded into the registers, either dot correction / clock divider ratio or luminance data. the remaining 30 bits are used for the data. this helps reduce the pin count of the A6280. to further lower the A6280 pin count, the pwm clock and the serial bus clock share the same pin and work concurrently to control led luminance and to load data. the A6280 is designed to minimize the number of components needed to drive leds with large pixel spacing. several A6280s can be daisy chained together and controlled by just four control signals (clock, serial data, latch, and output enable). each of these inputs has buffered outputs on chip. also, the vin pin A6280-ds, rev. 1 features and benefits ? 5 to 17 v operation ? wide output current range (10 to 150 ma per output) ? 3 7 bit dot correction current settings ? 31 bit shift register ? 3 10 bit pwm luminance settings ? buffered output control pins ? up to 5 mhz serial / pwm clock frequency ? thermal shutdown / uvlo 3 bit constant current led driver with pwm control continued on the next page? packages: 16 pin dip (suffix a), and 16 pin qfn/mlp (suffix es) application diagram es, approximate scale 1:1 A6280 clock data strobe output enable microprocessor control board clock out data out strobe out oe out clock in data in strobe in oe in v led out b out g out r v in power supply bus A6280 pixel board #1 r ext v reg clock out data out strobe out oe out clock in data in strobe in oe in v led out b out g out r v in A6280 pixel board #2 r ext v reg pixel board #n cat5 utp cat5 utp cat5 utp figure 1. functional drawing of daisy chained display application. additional pixel boards with A6280 ics can be applied.
3 bit constant current led driver with pwm control A6280 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com part number packing* mounting A6280ea-t 25 pieces/tube 16 pin dip A6280eestr-t 1500 pieces/reel 16 pin qfn/mlp *contact allegro for additional packing options. selection guide can be tied to the led voltage supply bus, thus eliminating the need for a separate chip supply bus or an external linear regulator. the A6280 is supplied in a 16 pin dual in line (dip) package (suffix ?a?) package and in a 16 lead qfn/mlp (suffix ?es?) package. the packages are lead (pb) free with 100% matte-tin leadframe plating. absolute maximum ratings characteristic symbol notes rating units supply voltage v in 17 v output voltage v o ?0.5 to 17 v output current i o 170 ma ground current i gnd 600 ma logic input voltage range v i ?0.3 to 7 v operating ambient temperature t a range e ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?40 to 150 oc description (continued) thermal characteristics characteristic symbol test conditions* rating units package thermal resistance r ja package a, 4 layer pcb 38 oc/w package es, 4 layer pcb 40 oc/w package es, 1 layer pcb with 1 in 2 . cu area 70 oc/w *for additional information, refer to the allegro website. 0 255075100125150 temperature (c) power dissipation, p d (mw) 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 power dissipation versus ambient temperature (r q ja = 38 oc/w) package a, 4 la yer pcb (r q ja = 40 oc/w) package es, 4 layer pcb (r q ja = 7 0 oc/w) package es, 1 lay er pcb
3 bit constant current led driver with pwm control A6280 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal list table name number description a package es package out1 1 11 sinking output terminal out0 2 12 sinking output terminal sdo 3 13 buffered serial data output after shift registers lo 4 14 buffered latch output oeo 5 15 buffered output enable output co 6 16 buffered clock output rext 7 1 an external resistor at this terminal establishes overall output current vreg 8 2 regulator decoupling lgnd 9 3 logic ground vin 10 4 chip power supply voltage ci 11 5 serial and pwm clock input oei 12 6 output enable input; when low (active), the output drivers are enabled; when high (inactive), all output drivers are turned off (blanked) li 13 7 latch input terminal; serial data is latched with high-level input sdi 14 8 serial data input to shift registers out2 15 9 sinking output terminal pgnd 16 10 power ground pin-out drawings package a package es out2 out1 out0 regulator current regulator 0 current regulator 1 current regulator 2 shift registers latched registers li sdi rext r ext lgnd pgnd ci lo sdo co oeo oei vin vreg functional block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pgnd out2 sdi li oei ci vin lgnd out1 out0 sdo lo oeo co rext vreg 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 co oeo lo sdo ci oei li sdi out0 out1 pgnd out2 rext vreg lgnd vin
3 bit constant current led driver with pwm control A6280 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com operating characteristics , valid at t a = 25c, v in = 4.75 to 17.0 v, unless otherwise noted characteristic symbol test conditions min. typ. max. units electrical characteristics quiescent supply current i dd f clkin = 0.0 hz ? ? 5.0 ma operating supply current i dd f clkin = 5 mhz ? ? 15.0 ma undervoltage lockout v in(uv) v in rising 3.5 ? 4.5 v v in falling 3.0 ? 4.0 v vreg voltage range v reg i o =15 ma, v in = 17 v 4.6 ? 5.4 v vreg dropout voltage v do i o =15 ma, v in = 4.75 v ? 200 600 mv output current (any single output) i o r ext = 5 k , scalar = 100% 135 150.0 165 ma r ext = 15 k 44 ? 54 ma output to output matching error* err output to output variation?all outputs on, r ext = 5 k 7? 7% output voltage range v ds(min) 1.0 ? 3.0 v load regulation i %diff / v ds ?13% output leakage current i dsx v oh = 17 v ? ? 1.0 a logic input voltage v ih 2.0 ? ? v v il ? ? 0.8 v logic input voltage hysteresis all digital inputs ? 150 ? mv logic input current i in v in = 0 to 5 v ?20 ? 20 a logic output voltage v ol v in 5.0 v, i o = 2 ma ? ? 0.4 v v oh 3.8 ? ? v input resistance r i oei pin, pull-up 150 300 600 k li pin, pull-down 100 200 400 k output dot correction error r ext = 5 k ; lsb ? 1 ? bit thermal shutdown temperature t jtsd temperature increasing ? 165 ? c thermal shutdown hysteresis t jhys ?15?c switching characteristics clock hold time t h(clk) 20 ? ? ns data setup time t su(d) 20 ? ? ns data hold time t h(d) 20 ? ? ns latch setup time t su(le) 20 ? ? ns latch hold time t h(le) 20 ? ? ns output enable set up time t su(oe) 40 ? ? ns output enable falling to outputs turning on propagation delay time t p(oe)2 ? 200 ? ns clock to output propagation delay time t p(out) v ds = 1.0 v, i o = 150 ma ? 200 ? ns logic output fall time t bf c ob = 50 pf, 4.5 to 0.5 v ? 50 100 ns logic output rise time t br c ob = 50 pf, 0.5 to 4.5 v ? 30 60 ns output fall time (turn off) t f c o = 10 pf, 90% to 10% of i o = 10 ma ? 10 ? ns c o = 10 pf, 90% to 10% of i o = 10 ma ? 10 ? ns output rise time (turn on) t r c o = 10 pf, 90% to 10% of i o = 10 ma ? 50 ? ns c o = 10 pf, 90% to 10% of i o = 10 ma ? 100 ? ns clock falling edge to serial data out propagation delay time t p(sdo) ? 50 100 ns output enable in to output enable out propagation delay t p(oe) ? 50 100 ns latch in to latch out propagation delay t p(le) ? 50 100 ns clock in to clock out propagation delay t p(clk) ? 50 100 ns clock out pulse duration t w(clk) 70 100 130 ns maximum clkin frequency f clkin ? ? 6 mhz *err = [i o (min or max) ? i o (av)] / i o (av).
3 bit constant current led driver with pwm control A6280 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 15 16 30 clock serial data in serial data out latch enable in latch enable out d30 d28 d27 d26 d25 d24 d23 d22 d8 d7 d0 d30 don?t care t w(clk) t su (d ) t h( d) t p(sd o ) t su (l e ) t h(le) t p( le) d29 pwm counter output enable in output enable out out0 luminance data= 0 out1 luminance data= 2 out2 luminance data= 1023 t p(o e ) t w(oe) t p(out) clock in t 0 0 1 2 1023 0 0 x t 1 t 2 t n t p( o u t) 1 2 t p(out) t p(out) 012345678 figure 2. shift register timing figure 3. pwm counter and output timing timing diagram
3 bit constant current led driver with pwm control A6280 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional description cur reg2 cur reg1 latch in output enable in clock in out rext 0 out 1 out 2 serial data out output enable out clock out serial data in latch out gnd cur reg0 shift registers gnd bit 30 ?1? ?0? latched registers 29 30 0 ??.. 9 10 ??.. 19 20 ??.. current scalar 0 7bits pwm counter 2 10 bits pwm counter 1 10 bits pwm counter0 10 bits clock divider 2bits unused 1bit current scalar 1 7bits unused 3bit vin regulator vreg current scalar 2 7bits test bit 1bit test bit 1bit unused 1bit figure 4. functional diagram shift registers the A6280 has a 31 bit shift register that loads data through the serial data in (sdi) pin. the shift registers operate by a first-in first-out (fifo) method. the most significant bit (msb, bit 30) is the first bit shifted in and the least significant bit (lsb, bit 0) is shifted in last. the serial data is clocked by a rising edge of the clock in (ci) pin. the serial data out (sdo) pin is updated to the state of bit 30 on the falling edge of the ci pin. this will prevent any race conditions and erroneous data that might occur while propagating information through multiple A6280 that are daisy chained together. the contents of the shift registers will continue to propagate on every rising edge of the ci pin. the information in the shift registers is latched on a rising edge of the latch in (li) pin. the latched data remains latched on a rising output enable in (oei) signal. output buffers the A6280 is designed to allow daisy chaining many A6280s together. it has the ability to pass the clock, data, latch, and out- put enable signals from one a6820 to the next without any loss of data due to duty cycle skewing or signal degradation. the a6820 is equipped with output buffers that allow the data signals to travel over long distances through strings of A6280s without the need for extra driving hardware. the A6280 drives these signals to ttl levels. each of the A6280 inputs have a cor- responding buffered output: ? clock in (ci) pin to clock out (co) pin ? latch in (li) pin to latch out (lo) pin ? output enable in (oei) pin to output enable out (oeo) pin ? serial data in (sdi) pin to serial data out (sdo) pin
3 bit constant current led driver with pwm control A6280 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com pwm luminance control the A6280 controls the intensity of each led by pwming the current of each output. the A6280 has three 10 bit luminance registers, one for each output. these luminance registers set the pwm count value at which the outputs switch off during each pwm cycle. each 10 bit luminance register gives 1023 levels of light intensity. the duty cycle, dc (%), can be determined by the following equation: dc = [(pwm n + 1 ) / 1024] 100 , where pwm n is the pwm value greater than zero that is stored in the luminance register. when the luminance register is set to zero, the outputs remain off for the duration of the pwm cycle for a 0% dc. when a luminance register is set to 1023, the led for that output remains on (100% dc) when oei is active and begins the pwm cycle. the output remains on when the pwm counter rolls over and begins a new count. the pwm counter begins counting at zero and increments only when the oei pin is held low. when the pwm counter reaches the count of 1023, the counter resets to zero and continues incrementing. the counter resets back to zero either on a rising edge of oei, upon recovery from uvlo, or when powering up. latching new data into the luminance registers will not reset the pwm counter. there is a programmable clock divider that attenuates the clock input of the ci pin. see table 1 for bit assignments of the programmable clock divider. the pwm counter is incremented on every rising edge of the ci pin divided by the clock divider count value when the oei pin is low. for example, if the clock divider is programmed to divide the ci by 2, then the pwm counter will increment once every 2 ci cycles. given a 5 mhz ci frequency, the clock period would be 200 ns. the clock divider data in the shift registers is latched on a rising edge of the latch in (li) pin. the latched clock divider data remains latched on a rising oei signal. the total number of possible colors of an rgb pixel is over 1 billion. refer to figure 6 for the mapping of shift register bits to latches. output current selection the overall maximum current is set by the external resistor, r ext , connected between rext and lgnd. once set, the maximum current remains constant regardless of the led volt- age variation, supply voltage variation, temperature, or other circuit parameters that could otherwise affect led current. the maximum output current can be calculated using the following equation: i o (max) = 753.12 / r ext . the relationship of the value selected for r ext and i o is shown in figure 5. internal linear regulator the A6280 has a built-in linear regulator. the regulator oper- ates from 5 to 17 v, and is intended to allow the vin pin of the A6280 to connect to the same supply as the leds. this will simplify board design by eliminating the need for a chip supply bus and external voltage regulators. the v reg pin is used by the internal liner regulator as an energy reservoir. this pin is for internal use only and is not intended as an external power source. the v reg pin should have a 1.0 f, 10 v ceramic capacitor connected between the v reg pin and lgnd. the capacitor should be located as close to the v reg pin as possible. table 1. clock divider configurations bits divide by count 78 0 0 1 (no division) 10 2 01 4 11 8 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 515253545556575 r ext (k ) i o (ma) figure 5. output current versus external resistor, r ext
3 bit constant current led driver with pwm control A6280 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com dot correction control the A6280 can further control the maximum output current for each output by setting the three 7 bit dot correction registers with scale data that ranges from 36.5% to 100% of the overall maxi- mum output current that is set by the r ext resistor. this feature is useful because not every type of led (red, green, or blue, for example) has the same level of brightness or intensity for any given current, and the brightness could be different even from led to led of the same type. by scaling the output currents so that all the leds have matched intensities, the application will have full color depth when using the pwm counters. the dot correction current can be calculated by the following equation: i o n = i o n (max) (scale n / 2 + 36.5) refer to figure 6 for the bit configurations for the scalar registers. the dot correction data in the shift registers is latched on a rising edge of the latch in (li) pin. the latched dot correction data remains latched on a rising oei signal. the default output cur- rent when the A6280 is powered up or recovers from a uvlo is 36.5% of the current set by the r ext resistor. package power dissipation the maximum allowable package power dissipation is deter- mined as: p d (max) = (150 ? t a ) / r ja . the actual package power dissipation is: p d(act) = dc 0 v ds0 i out0 + dc 1 v ds1 i out1 + dc 2 v ds2 i out2 + v in i in . when calculating power dissipation, the total number of avail- able device outputs is usually used for the worst-case situation (i.e., displaying all 3 leds at 100% dc). thermal shutdown (tsd) when the junction temperature of the A6280 reaches the thermal shutdown temperature threshold, t jtsd (165c typical), the outputs will shut off until the junction temperature cools down below the recovery threshold, ?t jtsd ? ? t j ( 15c typical). the shift registers and output latches will remain active during the tsd event. therefore there is no need to reset the data in the output latches. undervoltage lockout the A6280 includes an internal undervoltage lockout (uvlo) circuit that disables the driver outputs in the event of the logic supply voltage dropping below a minimum acceptable level. this prevents the display of erroneous information, a necessary function for some critical applications. the shift registers will not shift any data in a uvlo condition. upon recovery of the logic supply voltage and on power up, all internal shift registers and latches will be set to zero. ballast resistors the voltage on the outputs should be kept in the range 1 to 3 v. if the voltage goes below 1v, the current will begin to rolloff as the driver runs out of headroom. at v o above 3 v, the power dissipation may become a problem, as each output contributes v o i led of power loss in the output sink driver. typically the power supply nominal voltage is chosen to keep the output volt- age in this range. alternatively, series resistors can be added to dissipate the extra power and keep the output voltage within the recommended range. bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pwm counter 0 pwm counter 1 pwm counter 2 0 dot correction register 0 clock divider 0 dot correction register 1 000 dot correction register 2 0 atb* atb* 1 *allegro test bit (atb). reserved for allegro internal testing. always set to zero (0) in the application. figure 6. register configuration
3 bit constant current led driver with pwm control A6280 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com clock data strobe output enable system logic co oeo lo sdo A6280 es A6280 es maximum of 250 leds clock data strobe output enable system logic co oeo lo sdo A6280 es A6280 es maximum of 250 leds 16 15 14 13 5 9 tie lgnd and pgnd to pad externally 8.5 v 10 11 12 10 k 1 f x5r 10 f v o n 1 to 3 v 432 1 6 7 8 ci oei li pad sdi red leds green leds blue leds out2 pgnd out1 out0 rext vreg lgnd vin 16 15 14 13 5 9 10 v 10 11 12 5 k 1 f 10 v 10 f 75 v 2 0.5 w v o n 1 to 3 v 432 1 6 7 8 ci oei li pad sdi out2 pgnd out1 out0 rext vreg lgnd vin tie lgnd and pgnd to pad externally + C + C applications drawings figure 7. application driving 3 rgb leds at 75 ma peak figure 8. application driving high power led at 450 ma
3 bit constant current led driver with pwm control A6280 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a package, 16 pin dip .070 .045 1.78 1.14 .150 .115 3.81 2.92 .195 .115 4.95 2.92 .014 .008 0.36 0.20 .430 max 10.92 .015 min 0.38 .005 min 0.13 .280 .240 7.11 6.10 .775 .735 19.69 18.67 a b c seating plane .022 .014 .056 .036 16x .010 [0.25] m c .100 .2.54 .300 .7.62 .210 max 5.33 2 1 16 a preliminary dimensions, for reference only dimensions in inches metric dimensions (mm) in brackets, for reference only (reference jedec ms-001 bb) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area
3 bit constant current led driver with pwm control A6280 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com es package, 16 pin qfn/mlp the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. copyright?2006 allegromicrosystems, inc. 0.30 0.18 .012 .007 0.50 0.30 .020 .012 0.80 0.70 .031 .028 0.05 0.00 .002 .000 3.15 2.85 .124 .112 3.15 2.85 .124 .112 0.20 ref .008 a b c seating plane c 0.08 [.003] 16x 16x 0.10 [.004] m c a b 0.05 [.002] m c 0.50 .020 a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) preliminary dimensions, for reference only (reference jedec mo-220weed-4) dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p300x300x80-17w4m); adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 16 2 1 a 16 1 2 b 1.70 nom .067 1.70 nom .067 0.23 x 0.23 ref .009 x .009 1.70 nom .067 1.70 nom .067 0.30 nom .012 1 16 4x 12x 0.20 min .008 16x 0.20 min .008 0.50 nom .020 0.90 nom .035 0.20 min .008 3.10 nom .122 3.10 nom .122 c

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